Circuits commonly include MOS-based switches. For example, sampling circuits including input switches are commonly used at the front end of a circuit to receive and sample input signals. Specifically, analog-to-digital converters (ADCs) may include a sample-and-hold (or track-and-hold) circuit as an input switch for receiving analog input signals to be converted into digital codes. FIG. 1 illustrates a track-and-hold circuit as commonly known in the art. Referring to FIG. 1, the track-and-hold circuit 10 may include an input MOS transistor 12, a first set of switches 14, 16, 18, a second set of switches 20, 22, a voltage level shifter such as a capacitive level shifter (or a capacitor) 24, a load capacitor 26, a second MOS transistor 28, and an impedance 29. While MOS transistor 12 is illustrated as a NMOS for the convenience of discussion, MOS 12 may be a NMOS or PMOS transistor. MOS transistor 12 may include a gate (G), a source (S), and a drain (D). Additionally, MOS transistor 12 may include a back-gate (B) coupled to the body of the MOS 12. The MOS transistor 12 may operate alternatively in a first “track” phase (or, “ON” phase), controlled by a first clock (Φ1), during which MOS 12 is turned on and a second “hold” phase (or, “OFF” phase), controlled by a second clock (Φ2), during which MOS 12 is turned off. Voltage level shifter 24 is coupled between the gate (G) and source (S) of MOS 12 during the “track” phase via switches 14, 16. Gate (G) of MOS 12 is coupled to the ground (or a very low voltage level) during the “hold” phase via switch 20. Source (S) of MOS 12 may receive an input signal Vin which, in turn, may be generated from a voltage source Vs including a source impedance 29. Drain (D) of MOS 12 is coupled to a load capacitor 26 which is coupled to MOS switch 28 whose operating state is controlled by clock Φ1a. Back-gate (B) of MOS 12 is connected to the source (S) via a switch controlled by the first clock (Φ1) during the “track” phase, and is connected to a reference voltage such as ground (GND) via a switch 22 controlled by the second clock (Φ2) during the “hold” phase. Additionally, the track-and-hold circuit 10 may include parasitic capacitance Cp associated with MOS 12 at its source and drain. The parasitic capacitance Cp may also affect the quality of output signal Vsample.
Operating in the “track” phase when switches 14, 16, 18 are engaged according to clock Φ1 (Φ1 is high) and switches 20, 22 are disengaged according to clock Φ2 (Φ2 is low), MOS 12 (which is turned on) is connected to the input signal Vin through voltage level shifter 24 to bootstrap a voltage at the gate. Thus, if the bootstrapping voltage is VBSTRAP, the voltage at gate (G) during the “track” phase is VG=VBSTRAP+Vin. In this way, the output Vsample may sample (or track) Vin through the turned-on MOS 12. Further, switch 18 may also be engaged to couple back-gate (B) to source (S) according to the clock Φ1 to provide a back-gate bootstrapping to MOS 12. Next during the “hold” phase when switches 14, 16, 18 are disengaged according to clock Φ1 (Φ1 is low) and switches 20, 22 are disengaged according to clock Φ2 (Φ2 is high), the gate of MOS 12 is connected to ground (GND) (or a very low voltage level) to ensure MOS 12 is turned off. Thus, voltage at gate (G) during the “hold” phase is V′G≈0. Further, switch 22 may also be engaged to couple back-gate (B) to ground according to the clock Φ2.
While the back-gate bootstrapping may help keep the source-to-bulk voltage approximately constant (subjecting to the limitation of the source impedance Zs), the voltage swing (VG−V′G≈VBSTRAP S+Vin) at the gate of MOS 12 between the “track” and “hold” phases is dependent on the input signal Vin. Since the charge injection for the track-and-hold circuit 10 relates to voltage at the gate of MOS 12 and is therefore also dependent on input signal Vin. Charge injection is commonly understood as a voltage level change caused by parasitic capacitance (Cp) associated with NMOS or PMOS transistors in the track-and-hold circuit. When the charge injection is dependent on input signal Vin, it may cause further non-linearity in the output Vsample.
Another issue with the current art is that the gate (G) of MOS 12 is commonly grounded during the hold phase, while the source (S) and/or drain (D) of MOS 12 may reach high voltage values depending on the input signal (e.g., a sine wave). If the input signal causes the high voltages at the source (S) and/or drain (D) of MOS 12 exceed the maximum allowed values for MOS 12, the oxide of MOS 12 may break down, and the lifetime of the MOS 12 may be shortened.